1. Field of the Invention
This invention relates to semiconductor packages and more particularly to methods for hermetically sealing such packages and to the resultant hermetically sealed packages.
2. Description of Related Art
FIG. 1 is a schematic diagram of a cross-section of a fragment of a semiconductor module 10 of the kind shown in U.S. Pat. No. 6,046,074 of D. C. McHerron and H. T. Toy, commonly assigned, for xe2x80x9cHermetic Thin Film Metallized Sealband for SCM and MCM-D Modulesxe2x80x9d. FIG. 1 illustrates a common method of hermetically sealing a protective cap 12 (with a top 13 and with sides 27 which have vertical sidewalls 28) to a chip carrier 14 with a sealing structure 31 at the periphery of the chip carrier 14. The sealing structure 31 comprises a layer of solder 52 between a thin film (carrier) sealband 32 and a cap sealband 42. The cover and carrier sealbands 32/42, which are composed of sequentially applied thin metal sealing layers, are hermetically sealed together by the solder layer 52. The all metal peripheral sealing structure 31 transmits high stress to the top surface 14T of the chip carrier 14, due to the rigidity of the solder 52 and the sealbands 32/42 and due to the thermal expansivity mismatch between the metals in the sealing structure 31 and the chip carrier 14, e.g. a ceramic chip carrier. On the one hand, the chip carrier 14 can be composed of relatively strong materials such as alumina ceramics which are able to withstand the high stress. On the other hand, weaker materials such as glass-ceramics may develop stress cracks along the periphery of the seal 31 from sealing or from subsequent thermal cycling. Therefore, for such relatively weak materials as glass-ceramics, the problem is to devise a relatively inexpensive method for hermetically sealing a protective cap 12 to a chip carrier 14 where stress transmitted to the chip carrier 14 is a major issue.
Japanese Patent JP6140527 deals with hermetic sealing device component, wherein an AlN (Aluminum Nitride) circuit substrate is connected by brazing it to a metal frame while interposing a soft metal frame member.
IBM TDB Vol. 29, No. 11, April 1987, p 5088, of Arndt et al., xe2x80x9cFlexible Leaded Chip Carrierxe2x80x9d describes a second level attachment process for replacing pins with a flexible connection from TSM (Top Surface Mounted) surface pads which wind around the sides of the ceramic base plate (substrate) to the bottom of the ceramic base plate. A ceramic lid assures an hermetically sealed packagexe2x80x9d. A flexible polyimide (PI) lead minimizes stress on the surface solder board connection. The ceramic base plate provides dimensional stability.
U.S. Pat. No. 5,881,945, Edwards et al. xe2x80x9cMulti-Layer Solder Seal Band for Semiconductor Substrates and Processxe2x80x9d, commonly assigned, describes a multilayer three layer, all metallic sealing structure, but specifies all layers of the seal are metal in which the height of the seal is increased. The thick middle layer of the sealing structure, which has a relatively higher melting point than the outer layers, can be a lead/tin, lead/indium or tin/bismuth solder material. The top and bottom layers of the sealing structure, which have a relatively lower melting point than the middle layer can be lead/tin, lead/indium, or tin/bismuth solder materials. This makes the sealing structure more resistant to fatigue from CTE (Coefficient of Thermal Expansion) mismatch between the cap and the carrier. We have found that this type of sealing structure can cause substrate cracks adjacent to the seal band when a weaker substrate material such as glass-ceramic is used.
U.S. Pat. No. 5,201,456, Reynal et al. xe2x80x9cProcess for Assembly of a Metal Can on a Substrate Bearing an Integrated Circuitxe2x80x9d U.S. Pat. 5,201,456 teaches sealing a metal can to a substrate with a multi-layer seal. The metal can is formed by a metal frame with a metal cap sealed thereto by welding. The seal is comprised of a dielectric layer, a transition layer, and a metal layer. The transition layer is a mixture, of dielectric and metal (approximately 50/50). The purpose is to provide an xe2x80x9cair-tightxe2x80x9d, stress resistant seal and to provide electrical isolation of the lid from underlying conductive lines (xe2x80x9cstrip conductorsxe2x80x9d). The seal contains conductive lines.
U.S. Pat. No. 5,069,978 Mizuhara xe2x80x9cBrazed Composite Having Interlayer of Expanded Metalxe2x80x9d teaches brazing plates (e.g. chip carrier and cover) of dissimilar materials with a metal interlayer. The interlayer is formed into a slit, creased geometry, such that it offers a compliant connection, and is brazed on either side to the two plates. At any rate, it talks nothing about dual seal bands or polymers.
U.S. Pat. No. 4,315,591, Houston, xe2x80x9cMethod for Thermo-Compression Diffusion Bonding A Structured Copper Strain Buffer to Each Side of a Substrateless Semiconductor Waferxe2x80x9d teaches a thermo-compression diffusion bonding process whereby copper strain buffers are attached to opposite sides of a wafer.
IBM TDB Vol. 27, No. 3, (Aug. 1984) p 1701, of Olah et al. xe2x80x9cHermetic Seal for Semiconductor Packagexe2x80x9d describes a process for attaching non-metallic gaskets hermetically to porous substrates by mechanically clamping.
IBM TDB Vol. 27, No. 1A (June 1984), p. 129, of Bakos et al. xe2x80x9cMethod for Low Temperature Module Encapsulationxe2x80x9d describes a U-channel sealing scheme, with a low melt solder fill. The bismuth-based solder composition specified has a negative CTE, so that on cooling additional pressure is applied to the inside of the channel and the legs of the cap.
U.S. Pat. No. 5,931,222 of Toy, Edwards, Shih and Giri for xe2x80x9cAdhesion Promoting Layer for Bonding Polymeric Adhesive to Metal and a Heat Sink Assembly Using Samexe2x80x9d describes adhesion of a heat sink to the top surface of a nickel plated metal cap. The heat sink is adapted for cooling chips on a chip carrier. A hermetic sealing structure is formed at bottom edges of the cap which are nickel plated to the multi-chip carrier. A bottom seal band of nickel/gold layers is formed on the top surface of the chip carrier. The seal is formed by lead/tin solder between the nickel plated surface of the cap and the bottom seal band on the chip carrier. For the heat sink, the top of the cap is coated with a thin adhesion promoting metal film such as chromium or titanium. The heat sink is attached in a non-hermetic fashion to the thin adhesion-promoting metal film by a polymeric heat sink adhesive, such as a silicone elastomer material, which provides an interfacial bond between the top of the cap and a polymeric adhesive.
Previous glass-ceramic products which required hermetic sealing have used mechanical seals, such as solder coated C-rings. With associated required hardware, these tend to be more expensive and require more board real estate than the present invention. Also a C-ring seal requires an ultra-flat surface which translates to an expensive surface planarization process. In the present invention the thicker solder later (perhaps 100 micrometers) is able to absorb substrate out-of-flatness.
Unlike Japanese Patent JP6140527, this invention does not involve a frame, but replaces a xe2x80x9csoft metalxe2x80x9d (presumably a soft solder) with a thin stress-absorbent polymer, which is nearly hermetic, and can be made fully hermetic with a solder filled channel through the polymer.
As contrasted with U.S. Pat. No. 5,881,945, Edwards et al., a polymer layer is positioned adjacent to the chip carrier.
This invention differs from U.S. Pat. No. 5,201,456 of Reynal et al. in several regards as follows:
1. The surface to which sealing is made contains no conductive lines or features.
2. The seal contains just a polymer and metal without any transition layer.
3. This invention includes the option of having one layer xe2x80x9csharedxe2x80x9d by the metal and polymer via a channel.
Hermetic sealing has been an established art for the most common electronic chip carrier materials, but remains an expensive real-estate-costly process for glass-ceramic until this invention.
In accordance with this invention, a method is provided for forming a sealed electronic circuit package comprising the following steps. Provide a substrate having a top surface and a cover having a mating surface confronting the top surface of the substrate. Form a seal at the peripheral edge of the substrate between the substrate and the mating surface of the cover by the following steps. Forming a peripheral substrate non-metallic soft frame formed on the top surface of the substrate having a top soft frame surface which faces upwardly. Provide cover frame surface on the mating surface of the cover which is exposed downwardly. Form a lower adhesion frame over the soft frame, and join the top surface of the lower adhesion frame and the cover frame surface with solder to form a hermetic via-seal to the substrate frame surface forming a seal between the cover frame surface and the substrate.
One can employ a solder selected from the group consisting of an (SnAg or a SnAgCu solder with about 96%Sn) or a two-material (lead/tin eutectic) solder plus a polymer seal instead of a channel filled with solder.
Preferably, the solder has a melting point 30xc2x0 C. to 40xc2x0 C. below the melting point or the glass transition temperature Tg of any polymer or the melting point of any solder in the module or package.
Preferably, the channel and the via-seal are located laterally aside from the confronting portions of the surfaces of the cover and the substrate; the via-seal is exposed on the surface of the soft layer on an exterior surface of the peripheral substrate frame; or the via-seal is exposed on the surface of the soft layer on an interior surface of the peripheral substrate frame; the substrate is a ceramic chip carrier and the soft layer is a polymer; the substrate is a ceramic or glass ceramic chip carrier and the soft layer is a polymer, preferably polyimide; the lower adhesion frame is composed of laminated Crxe2x80x94Nixe2x80x94Au layers; the soft layer has a thickness preferably less than or equal to about 12 xcexcm.
Preferably, form the non-metallic soft frame with a central channel extending down through the non-metallic soft layer to expose a portion of the substrate frame surface below the channel with the lower adhesion frame extending down through the channel formed in the non-metallic soft layer to contact the substrate surface, whereby the hermetic via-seal extends through the channel to the substrate frame surface to form a seal between the cover frame surface and the substrate.
Preferably, form the lower adhesion frame with an extension across the edge of the non-metallic soft layer to contact the substrate surface at a distal location, so the hermetic via-seal extends across the edge of the soft layer to form a seal between the cover frame surface and the substrate.
In accordance with another aspect of this invention, the method comprises forming a sealed electronic circuit package by providing a substrate having a top surface and a cover having a mating surface confronting the top surface of the substrate. Form a seal at the peripheral edge of the substrate between the substrate and the mating surface of the cover by the following steps. Form a peripheral substrate non-metallic soft frame formed on the top surface of the substrate having a top soft frame surface which faces upwardly with a central channel formed down through the non-metallic soft layer to expose a portion of the substrate frame surface below the channel. Form a cover frame for providing adhesion formed on the mating surface of the cover, the cover frame having a cover frame surface which is exposed downwardly. Form a lower adhesion frame over the soft frame extending down through the channel formed in the non-metallic soft layer to contact the substrate surface. Join the top surface of the lower adhesion frame and the cover frame surface with solder and extending into the channel to form a hermetic via-seal through the channel to the substrate frame surface form a seal between the cover frame surface and the substrate extending through the channel in the soft frame.
One can employ a solder selected from the group consisting of an (SnAg or a SnAgCu solder with about 96%Sn) or a two-material (lead/tin eutectic) solder plus a polymer seal instead of a channel filled with solder.
Preferably, the solder has a melting point 30xc2x0 C. to 40xc2x0 C. below the melting point or the glass transition temperature Tg of any polymer or the melting point of any solder in the module or package.
In accordance with another aspect of this invention sealed electronic circuit package is provided comprising a substrate having a top surface, a cover having a mating surface confronting the top surface of the substrate, a seal at the peripheral edge of the substrate between the substrate and the mating surface of the cover. The seal includes a peripheral substrate non-metallic soft frame formed on the top surface of the substrate having a top soft frame surface which faces upwardly, a cover frame for providing adhesion formed on the mating surface of the cover, the cover frame having a cover frame surface which is exposed downwardly, a lower adhesion frame formed over the soft frame extending, and solder joining the top surface of the lower adhesion frame and the cover frame surface to form a hermetic via-seal.
Preferably the channel and the via-seal are located laterally aside from the confronting surfaces of the cover and substrate; with the via-seal exposed on the surface of the soft layer on an exterior surface of the peripheral substrate frame; the via-seal is exposed on the surface of the soft layer on an interior surface of the peripheral substrate frame; the substrate is a ceramic or glass ceramic chip carrier and the soft layer is a polymer preferably comprising polyimide; the lower adhesion frame is composed of laminated Crxe2x80x94Nixe2x80x94Au layers; and the soft layer has a thickness less than or equal to about 12 xcexcm. Preferably the non-metallic soft frame having a central channel formed down through the non-metallic soft layer to expose a portion of the substrate frame surface below the channel with the lower adhesion frame extending down through the channel formed in the non-metallic soft layer to contact the substrate surface, whereby the hermetic via-seal extends through the channel to the substrate frame surface to form a seal between the cover frame surface and the substrate. Preferably, the lower adhesion frame extends across the edge of the non-metallic soft layer to contact the substrate surface at a distal location, whereby the hermetic via-seal extends across the edge of the soft layer to form a seal between the cover frame surface and the substrate.
One can employ a solder selected from the group consisting of an (SnAg or a SnAgCu solder with about 96%Sn) or a two-material (lead/tin eutectic) solder plus a polymer seal instead of a channel filled with solder.
Preferably, the solder has a melting point 30xc2x0 C. to 40xc2x0 C. below the melting point or the glass transition temperature Tg of any polymer or the melting point of any solder in the module or package.
In accordance with another aspect of this invention, a sealed electronic circuit package comprises a substrate having a top surface, a cover having a mating surface confronting the top surface of the substrate, a seal at the peripheral edge of the substrate between the substrate and the mating surface of the cover, the seal including a)a non-metallic soft layer formed the top surface of the substrate for providing adhesion, at the peripheral edge of the substrate, the substrate frame having a top surface facing upwardly, b)a cover frame for providing adhesion formed on the mating surface of the cover having a cover frame surface facing downwardly, c) an intermediate adhesion layer formed on the upper surface of the soft layer, the intermediate adhesion layer having an upper surface, and d) solder formed between the intermediate adhesion layer upper surface and the cover frame surface.
Preferably the sealed electronic circuit package comprises a substrate having a top surface, a cover having a mating surface confronting the top surface of the substrate, a seal at the peripheral edge of the substrate between the substrate and the mating surface of the cover. The seal includes a) a peripheral substrate non-metallic soft frame formed on the top surface of the substrate having a top soft frame surface which faces upwardly with a central channel formed down through the non-metallic soft layer to expose a portion of the substrate frame surface below the channel, b) a cover frame for providing adhesion formed on the mating surface of the cover, the cover frame having a cover frame surface which is exposed downwardly, c) a lower adhesion frame formed over the soft frame extending down through the channel formed in the non-metallic soft layer to contact the substrate surface, and d) solder joining the top surface of the lower adhesion frame and the cover frame surface and extending into the channel to form a hermetic via-seal through the channel to the substrate frame surface form a seal between the cover frame surface and the substrate extending through the channel in the soft frame.